1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to integrated semiconductor devices, such as complementary metal oxide semiconductor (CMOS) devices.
2. Description of the Related Art
In CMOS integration, i.e. NMOS and PMOS on the same chip, at least one well is needed on a silicon substrate. For example, when using a p-type substrate, NMOS can be fabricated on the substrate, while PMOS must be fabricated on an n-well in the substrate. Alternatively, when using an n-type substrate, PMOS can be fabricated on the substrate, while NMOS must be fabricated on a p-well in the substrate. Further, in order to avoid problems associated with latch-up, a dual-well approach is usually employed. The dual-well approach involves forming NMOS on a p-well and PMOS on an n-well, regardless of the type of starting substrate. The dopant concentrations of both wells are tailored so that the latch-up situation does not occur.
In order to completely isolate both wells from the starting substrate, one extra well is often employed. This is called the “triple-well” structure. In this case, for example, when an n-well is formed in an n-type substrate, unless the bottom and the surrounding of the n-well is sealed by p-dopant material, it is not possible to isolate the n-well and bias it differently from the substrate. One common example is the formation of a DRAM array having NMOS transfer gates on a p-doped silicon substrate. Without using a triple-well structure, the DRAM array can not be biased with a voltage which is different from ground. A negative bias “Vbb” is generally applied to the buried well so that charge retention can be preserved. Triple well structures are also desirable for placing analog devices which either generate either a high level of noise, or demand a very quiet environment, and are also applicable to devices or circuits which require a separate body bias.
A great challenge in well formation has been experienced as CMOS technology is scaled beyond deep sub-micron and into the nanometer groundrule regime. As devices are getting smaller, the ground rules such as well-to-well and device-to-well dimensions are also expected to scale accordingly. However, the same scaling factors which apply to the transistor may not apply to conventional wells which are formed by ion implantation. One problem associated with using ion implantation to form wells is the well proximity effect, wherein the doping profile at the edges of a well is not uniform across the breadth of the well. This phenomenon is due to ion scattering from high energy, high dose ion implantation. As a result, devices that are disposed closer to the edges of a well have a different threshold voltage Vt than devices disposed away from the edges of the well. One simple solution to this problem is to keep devices away from the edges of the wells. However, this approach is not suitbale in a 6-T SRAM array where memory cells must be closely packed. Specifically, keeping devices away from the edges of wells obviously wastes chip space, and if the resultant threshold voltage is unacceptable to the SRAM cell, then an additional mask must be added to the process to properly center the threshold voltage, resulting in additional cost and complexity.